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71M6545/71M6545H Data Sheet
Name
Location
Rst Wk Dir
Description
FLSH_PWE
FLSH_RDE
FLSH_UNLOCK[3:0]
FLSH_WRE
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
INTBITS
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
MPU_DIV[2:0]
MUX0_SEL[3:0]
MUX1_SEL[3:0]
SFR B2[0]
2702[2]
2702[7:4]
2702[1]
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[3]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[6]
SFR F8[5]
2707[6:0]
2887[6:0]
2887[7]
2888[7:0]
2889[1]
2889[0]
2200[2:0]
2105[3:0]
2105[7:4]
0
–
0
–
0
–
0
0
0
0
0
0
0
0
0
–
0
–
0
–
0
0
0
0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @ DPTR ,A moves A to External Program Space (Flash) @ DPTR .
This bit is automatically reset after each byte written to flash. Writes to this bit are
inhibited when interrupts are enabled.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (! SECURE )
Must be a 2 to enable any flash modification. See the description of Flash security
for more details.
Indicates that the flash may be written through ICE or SPI slave ports.
Interrupt flags for external interrupts 2 and 6. These flags monitor the source of the
int6 and int2 interrupts (external interrupts to the MPU core). These flags are set by
hardware and must be cleared by the software interrupt handler. The IEX2 ( SFR
0xC0[1] ) and IEX6 ( SFR 0xC0[5] ) interrupt flags are automatically cleared by the MPU
core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing
zero to their corresponding bit positions in SFR 0xC0, while writing ones to the other
bit positions that are not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external interrupts
INT0, INT1, up to INT6. These bits do not have any memory and are primarily
intended for debug use.
The address for reading and writing the RTC lookup RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD
or LKP_WR is pulsed. The incremented address can be read at LKPADDR.
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0]
and LKPDAT registers is used in a read or write operation. When a strobe is set, it
stays set until the operation completes, at which time the strobe is cleared and
LKPADDR[6:0] is incremented if LKPAUTOI is set.
MPU clock rate is:
MPU Rate = MCK Rate * 2 -(2+ MPU_DIV [2:0]) .
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the
PLL_FAST bit and MPU_DIV[2:0] , the power up MPU rate is 4.92MHz * ? = 1.23 MHz.
The minimum MPU clock rate is 38.4 kHz when PLL_FAST = 1.
Selects which ADC input is to be converted during time slot 0.
Selects which ADC input is to be converted during time slot 1.
92
v2
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